1. Technical Field
This invention relates generally to semiconductor devices, and more particularly, to semiconductor devices wherein a self-aligned source (SAS) etch is undertaken and a common source line is formed in a memory array.
2. Background Art
Reference is made to FIGS. 1–5, which illustrate a typical version of particular steps in undertaking a self aligned source (SAS) etch. As shown in FIG. 1, a silicon substrate 20 has thereon adjacent gate stacks 22, 24 formed by well-known processing steps. Each gate stack includes a tunnel oxide 26, a polysilicon floating gate 28, a dielectric, for example ONO layer 30, and a polysilicon word line 32, all as is well-known. Next, an oxide layer 34 is formed on the resulting structure, as shown in FIGS. 2 and 3, covering oxide isolation regions 36 in trenches 38 formed in the substrate 20, the gate stacks 22, 24, and the silicon substrate 20 between the gate stacks 22, 24. After formation of a patterned photoresist mask 40, an anisotropic etch of the exposed oxide is undertaken to form spacers 42, 44 on the adjacent sides of the gate stacks 22, 24, in preparation for undertaking a self aligned source etch. A purpose of the spacers 42, 44 is to protect the silicon underneath the tunnel oxide (FIG. 4) from being gouged during the self aligned source etch, which, without such spacers 42, 44, can result in severely degrading the erase integrity and erase distribution of the device.
As will be seen, the self aligned source etch must be undertaken for a substantial time in order to completely etch through the thick oxide isolation regions 36 (FIG. 5) in preparation for providing a common source line to connect the sources of the device. It has been found that, during such substantial self aligned source etching step, some of the oxide spacer 22, 24 material is laterally etched away during this process, allowing the etchant closer to the silicon substrate 20 adjacent the tunnel oxide 26 than is desirable. This reduces the effectiveness of the spacers 42, 44 in preventing the gouging of the silicon substrate 20 as described above.
Another problem arises with regard to the formation of a common source line once the self-aligned source etch has been undertaken. Typically, an ion implantation step is undertaken to form the common source line, the width of the line being determined by the spacing between the spacers. As is well known, it is desirable to scale, i.e., decrease the dimensions of conventional memory cells in order to increase their density in the memory array. In doing so, the formed source line becomes narrower, so that without adjustments in the process, common source line resistance increases.
Therefore, what is needed is a method for reducing gouging of the silicon substrate near the tunnel oxide of a flash memory device by ensuring the integrity of spacers on the sidewalls of the stacked gates during the self aligned source etch. What is further needed is a process for forming a common source line of very low resistance so that device scaling is promoted.